mike@mike-desktop:/tmp/Viewer$ lsusb -d 03eb:6124
Bus 005 Device 040: ID 03eb:6124 Atmel Corp. at91sam SAMBA bootloader

mike@mike-desktop:~/ARM/sam-ba_cdc_2.8.linux_01$ ./sam-ba_cdc_2.8.linux_01
-I- Waiting ...
-I- TCL platform : Linux
-I- SAM-BA OS : linux
-I- Search for device decription files in folder :
-I- /home/mike/ARM/sam-ba_cdc_2.8.linux_01/sam-ba_cdc_2.8.linux_01/../lib/devices
-I- Reading AT91SAM9263.tcl
-I- Check the processor ID at address : 0xFFFFEE40
-I- Read chip ID : 0x00000010 at addr: 0xFFFFEE40
-I- Reading AT91SAM7S32.tcl
-I- Check the processor ID at address : 0xFFFFF240
-I- Read chip ID : 0x019803A1 at addr: 0xFFFFF240
-I- Found device : AT91SAM9260 (Chip ID : 0x019803A0)

loading history file ... 0 events added
SAM-BA console display active (Tcl8.4.17 / Tk8.4.17)
(sam-ba_cdc_2.8.linux_01) 1 %
(sam-ba_cdc_2.8.linux_01) 1 % DATAFLASH::SelectDataflash AT91C_SPI0_CS0
-I- Init SPI0 for DataFlash interfaces
-I- Configure SPI0 PIOs
-I- Reset the SPI0
-I- Configure SPI0 in Master Mode (no CS selected)
-I- Configure SPI0 CS0 for DataFlash AT45
-I- Configure SPI0 CS1 for DataFlash AT45
-I- Disable the RX and TX PDC transfer requests
-I- Reset all Counter register Next buffer first
-I- Enable the RX and TX PDC transfer requests
-I- End of Init_DataFlash
-I- Switch to the correct PCS of SPI0 Mode Register (Fixed Peripheral Selected)
-I- Chip Select 0 Selected
-I- Enable the SPI0
-I- Wait for dataflash ready (bit7 of the status register)
-I- DataFlash AT45DB321
-I- End of Select DataFlash
-I- Initialize SDRAM
-I- Configure PIOC as peripheral (D16/D31)
-I- Init MATRIX to support EBI0 CS1 for SDRAM
-I- Init SDRAM
-I- 1. A minimum pause of 200us is provided to precede any signal toggle
-I- 2. A Precharge All command is issued to the SDRAM
-I- *pSDRAM = 0;
-I- 3. Eight Auto-refresh are provided
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- *pSDRAM = 0;
-I- 4. A mode register cycle is issued to program the SDRAM parameters
-I- *(pSDRAM+0x20) = 0;
-I- 5. Write refresh rate into SDRAMC refresh timer COUNT register
-I- 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
-I- *pSDRAM = 0;
-I- End of Init_SDRAM_48
(sam-ba_cdc_2.8.linux_01) 1 % DATAFLASH::SendBootFileGUI
-I- File size = 3432 byte(s)
-I- Boot File Written Successfully
(sam-ba_cdc_2.8.linux_01) 1 %

# lspci | grep USB
00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 01)
00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 01)
00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 01)
00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 01)
00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 01)

00:1a.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 02)
00:1a.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 02)
00:1a.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 02)
00:1d.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 02)
00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 02)