недели через 2-3.

По распиновкам чипов есть что сказать

static iomux_v3_cfg_t mvf600_pads[] = {

/*SDHC1*/
MVF600_PAD14_PTA24__SDHC1_CLK,
MVF600_PAD15_PTA25__SDHC1_CMD,
MVF600_PAD16_PTA26__SDHC1_DAT0,
MVF600_PAD17_PTA27__SDHC1_DAT1,
MVF600_PAD18_PTA28__SDHC1_DAT2,
MVF600_PAD19_PTA29__SDHC1_DAT3,
/* sdhc card detecting*/
MVF600_PAD36_PTB14__SDHC1_SW_CD,

/*I2C1*/
MVF600_PAD132_PTE27__I2C1_SCL,
MVF600_PAD133_PTE28__I2C1_SDA,

/*CAN1*/
MVF600_PAD38_PTB16__CAN1_RX,
MVF600_PAD39_PTB17__CAN1_TX,

/*DSPI1*/
MVF600_PAD84_PTD5__DSPI1_PCS0,
MVF600_PAD81_PTD2__DSPI1_PCS3,
MVF600_PAD85_PTD6__DSPI1_SIN,
MVF600_PAD86_PTD7__DSPI1_SOUT,
MVF600_PAD87_PTD8__DSPI1_SCK,

/*FEC0*/
MVF600_PAD40_PTB18__CCM_CKO1,
MVF600_PAD0_PTA6__RMII_CLKIN,
MVF600_PAD45_PTC0__RMII0_MDC,
MVF600_PAD46_PTC1__RMII0_MDIO,
MVF600_PAD47_PTC2__RMII0_CRS_DV,
MVF600_PAD48_PTC3__RMII0_RXD1,
MVF600_PAD49_PTC4__RMII0_RXD0,
MVF600_PAD50_PTC5__RMII0_RXER,
MVF600_PAD51_PTC6__RMII0_TXD1,
MVF600_PAD52_PTC7__RMII0_TXD0,
MVF600_PAD53_PTC8__RMII0_TXEN,
MVF600_PAD42_PTB20__PHY_RST,

/*UART*/
MVF600_PAD32_PTB10_UART0_TX,
MVF600_PAD33_PTB11_UART0_RX,

MVF600_PAD28_PTB6_UART2_TX,
MVF600_PAD29_PTB7_UART2_RX,

MVF600_PAD10_PTA20_UART3_TX,
MVF600_PAD11_PTA21_UART3_RX,
};

sasamy

So, it looks like the summary is to use 3 possible workarounds to fix the timing:

1. Which you already proved - using an additional Vybrid IO to output 50MHz clock to be used by both Vybrid PTA6 pins and the PHY (IMO, the most straightforward one),

Если сеткой решили заниматься - обратите внимание на тактирование Ethernet RMII - тактируется ENET с встроенного PLL но через внешний пин

Да