#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <mach/at91_tc.h>
#include <asm/uaccess.h>

//g++ -Wall -c "%f"
//g++ -Wall -o "%e" "%f"

struct file_operations at91adc_fops;

void __iomem *at91tc0_base;
struct clk *at91tc0_clk;

/************************************************************************************
| Timer counter 0 ISR:
*************************************************************************************/
static int status;
static int Counter;
static int y=0;

static irqreturn_t at91tc0_isr(int irq, void *dev_id)
{
// Read TC0 status register to reset RC compare status.
status = ioread32(at91tc0_base + AT91_TC_SR);

if(y<10)
{
y++;
Counter = ioread32(at91tc0_base + AT91_TC_CV);//
printk(KERN_INFO "Counter = %d\n", Counter);
}
else {
y=20;
//printk(KERN_INFO "Init 1000\n");
//Counter = ioread32(at91tc0_base + AT91_TC_CV);//
//printk(KERN_INFO "Counter = %d\n", Counter);
//clk_disable(at91tc0_clk);
}

return IRQ_HANDLED;
}

int init_at91clk(void)
{
printk(KERN_INFO "Init 0\n");
int ret=0;
//Initialize Timer Counter module 0. The following two lines set the appropriate
//PMC bit for TC0. Easier than mapping PMC registers and then setting the bit.
at91tc0_clk = clk_get(NULL, // Device pointer - not required.
"tc0_clk"); // Clock name.

printk(KERN_INFO "Init 1\n");
clk_enable(at91tc0_clk);
printk(KERN_INFO "Init 2\n");

// Map TC0 registers to the current address space.
at91tc0_base = ioremap_nocache(AT91SAM9260_BASE_TC0, // Physical address
64); // Number of bytes to be mapped.
if (at91tc0_base == NULL)
{
printk(KERN_INFO "at91adc: TC0 memory mapping failed\n");
ret = -EACCES;
return ret;
}

printk(KERN_INFO "Init 3\n");
// Configure TC0 in waveform mode, TIMER_CLK1 and to generate interrupt on RC compare.
// Load 50000 to RC so that with TIMER_CLK1 = MCK/2 = 50MHz, the interrupt will be
// generated every 1/50MHz * 50000 = 20nS * 50000 = 1 milli second.
// NOTE: Even though AT91_TC_RC is a 32-bit register, only 16-bits are programmble.

iowrite32(50000, (at91tc0_base + AT91_TC_RC));
iowrite32((AT91_TC_WAVE | AT91_TC_WAVESEL_UP_AUTO), (at91tc0_base + AT91_TC_CMR));
iowrite32(AT91_TC_CPCS, (at91tc0_base + AT91_TC_IER));
printk(KERN_INFO "Init 4\n");

// Install interrupt for TC0.
ret = request_irq(AT91SAM9260_ID_TC0, // Interrupt number
at91tc0_isr, // Pointer to the interrupt sub-routine
0, // Flags - fast, shared or contributing to entropy pool
"at91adc", // Device name to show as owner in /proc/interrupts
NULL); // Private data for shared interrupts

if (ret != 0)
{
printk(KERN_INFO "at91adc: Timer interrupt request failed\n");
ret = -EBUSY;
return ret;
}
printk(KERN_INFO "Init 5\n");
iowrite32((AT91_TC_SWTRG | AT91_TC_CLKEN), (at91tc0_base + AT91_TC_CCR));//timer start

printk(KERN_INFO "at91adc: Timer starting adn Module louded\n");
return 0;
}


void exit_at91clk(void)
{
clk_disable(at91tc0_clk);

// Free TC0 IRQ.
free_irq(AT91SAM9260_ID_TC0, // Interrupt number
NULL); // Private data for shared interrupts

iounmap(at91tc0_base);
printk(KERN_INFO "at91adc: Unloaded module\n");
}

module_init(init_at91clk);
module_exit(exit_at91clk);

MODULE_LICENSE("GPL");

# Если KERNELRELEASE определен, вызов был произведен из
# из системы сборки ядра и мы можем пользоваться её языком.
ifneq ($(KERNELRELEASE),)
obj-m := firstmodule.o
obj-m := at91clk.o

# Иначе, вызов был из командной строки;
# вызываем систему сборки.
else

#KERNELDIR ?= /lib/modules/$(shell uname -r)/build #/home/xxx/buildroot-2011.05/output/build/linux-2.6.33/
KERNELDIR ?= /home/xxx/buildroot-2011.05/output/build/linux-2.6.33/

PWD := $(shell pwd)
default:
$(MAKE) ARCH=arm CROSS_COMPILE=/home/xxx/buildroot-2011.05/output/host/usr/bin/arm-unknown-linux-uclibcgnueabi- -C $(KERNELDIR) M=$(PWD) modules


endif

if(y<10)
{
y++;
Counter = ioread32(at91tc0_base + AT91_TC_CV);//
printk(KERN_INFO "Counter = %d\n", Counter);
}

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